The present invention relates to an access control unit. More particularly, the invention relates to an access control unit for a memory device, expecially the memory device of a data processing system having an interleaved memory unit wherein if the contents of the cycle designation counter which sequentially instructs the several memory units does not coincide with the memory unit indicated by the address information and to be accessed, such address information is temporarily held. This provides control, so that instruction by the contents of the cycle designation counter coincides with the memory unit to be accessed.
When the machine cycle speed of the data processor of a microprogram data processing system becomes high, for example, the cost of a control memory device having an access time fast enough to satisfy the aforementioned cycle speed increases. A method is thus desired which assures the same effect as that of the high speed cycle time with a memory having a slower speed access cycle time. An interleaved method is utilized as the aforedescribed method. In such method, the control memory device is divided into two control memory units, for example, divided into two banks. Access is undertaken alternately for each bank and the micro instructions are read out equivalently for every machine cycle. In this case, the following methods are undertaken in order to provide a smooth execution.
1. The microprogram is designed so that access is always undertaken alternately for both banks. PA1 2. The address is always supervised, and when an access request is issued twice in succession to the same bank, the previous access to the bank is undertaken and then the next access is made at such time to the same bank.
The first method is considerably difficult to form a program, so that access to the bank is always undertaken alternately. Moreover, in the second method, the access time becomes slow, since the bank to be accessed is determined after confirming the address, and it is also difficult to provide a timing when access is made in succession to the same bank.
An object of the invention is to overcome the aforedescribed disadvantages. In order to accomplish this, the access starting cycle of both banks is fixed and the address is alternately supplied to both banks without any requirement. On the other hand, when the bank designated by the address does not coincide with the bank accessed practically, the erroneous data is invalidated.
In this method, the bank to be accessed is not determined after confirming the address, but access is always undertaken alternately at an arbitrarily specified period. Therefore, a higher speed is provided than that in the second method. However, when access is requested twice in succession of the same bank, the second access is requested of the bank in the opposite side. Therefore, the resultant erroneous data is invalidated and access is undertaken to the correct bank by trial with the same address. As a result, the time for one cycle is wasted. However, a higher speed than that in the second method is obtained when such access to the same bank in succession is not undertaken so often.
Furthermore, the microprogram may be designed more freely than in the first method. For this purpose, the access control unit of the present invention is used in data processing equipment providing several control memory units which store instructions, are accessed in common, and are interleaved. A cycle designation counter which instructs in succession the access for the control memory unit, and address holding register, and an access comparison detection means which detects non-coincidence between the contents of the counter and access for the particular aforedescribed control memory unit, are provided. The control provided is such that the processing of instructions read out is invalidated during the relevant cycle at a previously determined cycle time, while non-coincidence is detected by the access comparison detection means.